The present invention generally relates to a bus controller, and, more particularly, to a bus controller for arbitrating access requests of a plurality of microcontrollers to a shared memory.
A bus controller is provided between a plurality of microcontrollers and a memory. The bus controller arbitrates access requests from respective microcontrollers to the shared memory and generally sequentially provides access authority to the microcontroller having a highest priority. The bus controller provides a bus wait signal to the microcontrollers having a lower priority. The microcontrollers having the lower priority wait until the processing operation of the microcontroller having the higher priority terminates, at which time the bus controller again determines which microcontroller will be granted access to the memory.
FIG. 1 is a schematic block diagram of a conventional bus controller. A memory controller (bus controller) 50 is connected to first and second microcontrollers 51 and 52 via CPU buses 53 and 54. Each of the microcontrollers 51 and 52 supplies an access signal such as a read instruction or a write instruction to the memory controller 50. Now, assume the first microcontroller 51 has a higher priority than the second microcontroller 52. When the access requests are made from the first and second microcontrollers 51 and 52 to the memory controller 50, the memory controller 50 controls a memory 55 in accordance with the access request from the first microcontroller 51. For example, the memory controller 50 reads data from the memory 55 in accordance with a read access request of the first microcontroller 51 and temporarily stores the data in a data buffer 50a and then supplies the stored data to the first microcontroller 51 via the CPU bus 53. The memory controller 50 further lowers a bus wait signal RDY supplied to the second microcontroller 52 from an H level (high potential or logical value "1") to an L level (low potential or logical value "0"). The second microcontroller 52 waits in response to the bus wait signal RDY low.
FIG. 2 is a timing chart explaining the operation of the memory controller 50 and the second microcontroller 52. The memory controller 50 receives a read signal RD low for a read operation supplied from the second microcontroller 52 and in return, supplies the bus wait signal RDY low to the second microcontroller 52. The second microcontroller 52 supplies the read instruction to the memory controller 50 and waits.
When the transfer of the data read from the memory 55 to the first microcontroller 51 has terminated, the memory controller 50 then controls the memory 55 in accordance with the read instruction from the second microcontroller 52. At this time, the memory controller 50 raises the bus wait signal RDY from an L level to an H level. The second microcontroller 52 resets the wait state in response to the bus wait signal RDY high and receives read data from the data buffer 50a. The second microcontroller 52 cannot receive read data from the data buffer 50a while it is waiting. As a result, the efficiency of the second microcontroller 52 is reduced. In particular, when an access request is made from another microcontroller having a higher priority than the second microcontroller 52 while the second microcontroller 52 is waiting, the wait time of the second microcontroller 52 is prolonged, such that it may enter a bus locked state.
It is an object of the present invention to provide a bus controller that improves the processing efficiency of microcontrollers.